The book is devoted to the design of digital systems using high-level Hardware Description Language (HDL) - Verilog and VHDL. These languages ​ ​ are an international standard and are used both by analysis systems (modeling) and by systems for synthesizing digital equipment. The basic concepts of these languages ​ ​ are presented from a single position. Recommendations on coding style, synthesizability and verification of HDL descriptions of designed systems are given. Examples of synthesizable descriptions of nodes and devices and the organization of functional tests are given.