The book is dedicated to SystemVerilog, the hardware description language used to model electronic systems. The developers of SystemVerilog made its syntax similar to the syntax of the C language, which makes it easier to master. In modern approaches to the design of equipment, model verification (verification) is no less important than its development. SystemVerilog offers designs that better reflect engineering intent in models, software abstractions that simplify the development of test environments, statements that verify the behavior of complex systems, and means of measuring functional coverage during the verification process. A description of the language is given along with material on logical design, so that the book can be used as a tutorial for digital circuitry and computer architecture courses. The publication will be useful for students taking an introductory course in digital circuitry, as well as developers who are familiar with Verilog or VHDL, but want to refresh their skills or need a quick reference for SystemVerilog. It is assumed that the reader has basic training in circuitry and programming.